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ISL88042
Data Sheet June 8, 2009 FN6655.1
Quadruple Voltage Monitor
The ISL88042 is a Quadruple voltage-monitoring supervisor combining competitive reset threshold accuracy and low power consumption. This device combines popular functions such as Power-On Reset, Undervoltage Supply Supervision, reset signaling and Manual Reset. Monitoring four different supplies in a 8 Ld 2x3 TDFN package, the ISL88042 devices can help to lower system cost, reduce board space requirements, and increase the reliability of multi-voltage systems. Low VDD detection circuitry protects the user's system from low voltage conditions, resetting the system when VDD or any of the other monitored power supply voltages fall below their respective minimum voltage thresholds. The reset signal remains asserted until all of these voltages return to proper operating levels and stabilize. Two of the four voltage monitors have preset thresholds for either dual 3.3V or one each for one 5V and one 3.3V supplies. Users can adjust the threshold voltages of the third and fourth voltage monitors in order to meet specific system level requirements.
Features
* Quadruple Voltage Monitoring * Fixed-Voltage Options Allow Precise Monitoring of +5.0V and +3.3V Power Supplies * Two Adjustable Voltage Inputs Monitor Voltages > 0.6V * 95ms Nominal Reset Pulse Width * Manual Reset Capability * Reset Signals Valid Down to VDD = 1V * Immune to Power-Supply Transients * Low 22A Maximum Supply Current at 5V * Pb-Free (RoHS Compliant)
Applications
* Telecom and Datacom Systems * Routers and Servers * Access Concentrators * Cable/Satellite Applications * Desktop and Notebook Computer Systems
Pinout
ISL88042 (8 LD TDFN) TOP VIEW
MR VDD V2MON GND 1 2 3 4 EPAD 8 7 6 5 RST VDDA V4MON V3MON
* Data Storage Equipment * Set-Top Boxes * Industrial Equipment * Multi-Voltage Systems
(GND)
Ordering Information
PART NUMBER (Notes 1, 2) ISL88042IRTHFZ-T ISL88042IRTHFZ-TK ISL88042IRTEEZ-T ISL88042IRTEEZ-TK ISL88042IRTJJZ-T ISL88042IRTJJZ-TK NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART MARKING 4P6 4P6 2P9 2P9 2P8 2P8
VTH1 (V) 4.60 4.60 2.87 2.87 2.78 2.78
VTH2 (V) 3.09 3.09 2.95 2.95 2.86 2.86
TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85
PACKAGE Tape & Reel (Pb-free) 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN
PKG. DWG. # L8.2x3A L8.2x3A L8.2x3A L8.2x3A L8.2x3A L8.2x3A
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL88042 Pin Descriptions
ISL88042 PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME MR VDD V2MON GND V3MON V4MON VDDA RST FUNCTION Active-Low open drain manual reset input with internal pull-up resistor Chip Bias Input and primary integrated preset undervoltage monitor Secondary integrated preset undervoltage monitor input Ground Adjustable undervoltage monitor input Adjustable undervoltage monitor input Must be tied to VDD for proper operation Active-low open drain reset output
Functional Block Diagram
VDD MR POR VREF PB
RST V2MON
tPOR
V4MON
VREF
VREF
V3MON
GND VREF
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ISL88042
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40C to +125C Voltage on VDD with Respect to GND. . . . . . . . . . . . . . -1.0V to +7V Voltage on V3MON, V4MON . . . . . . . . . . . . . . . . . . . . . . -1.0V to 3V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . -1.0V to VDD + 0.3V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 8 Ld TDFN Package (Notes 3, 4). . . . . 60 8 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature Range (Industrial) . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEST CONDITIONS MIN 2.0 VDD = 5.0V V2MON = 3.3V V3MON, V4MON = 1.0V 14 5.5 19 TYP MAX 5.5 22 8 100 UNITS V A A nA
SYMBOL VDD IDD1 IDD2 IDDA
PARAMETER Supply Voltage Range VDD Supply Current V2MON Input Current V3MON, V4MON Input Current
VOLTAGE THRESHOLDS VTH1 Fixed Voltage Trip Point for VDD ISL88042IRTHFZ ISL88042IRTEEZ ISL88042IRTJJZ VTH1HYST Hysteresis of VTH1 VTH1 = 4.60V VTH1 = 2.87V VTH1 = 2.78V VTH2 Fixed Voltage Trip Point for V2MON ISL88042IRTHFZ ISL88042IRTEEZ ISL88042IRTJJZ VTH2HYST Hysteresis of VTH2 VTH2 = 3.09V VTH2 = 2.96V VTH2 = 2.86V VREF VREF VREFHYST RESET VOL Reset Output Voltage Low VDD 3.3V, Sinking 2.5mA VDD < 3.3V, Sinking 1.5mA tRPD VTH to Reset Asserted Delay 0.05 0.05 6 0.40 0.40 V V s ISL88042IRTHFZ, ISL88042IRTEEZ Adj. Reset Threshold Voltage VTH for V3MON, V4MON 0.572 0.554 2.936 2.815 2.725 4.370 2.734 2.647 4.600 2.872 2.78 92 58 58 3.090 2.957 2.86 61 60 60 0.600 0.581 12 0.630 0.610 V V mV 3.245 3.099 3.000 4.830 3.010 2.914 V V V mV mV mV V V V mV mV
ISL88042IRTJJZ Adj. Reset Threshold Voltage VTH for V3MON, V4MON Hysteresis Voltage
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ISL88042
Electrical Specifications
Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEST CONDITIONS V3MON, V4MON < 3V MIN 40 TYP 95 MAX 150 UNITS ms
SYMBOL tPOR
PARAMETER POR Timeout Delay
MANUAL RESET VMRL VMRH tMR RPU MR Input Voltage Low MR Input Voltage High MR Minimum Pulse Width Internal Pull-Up Resistor
.
0.8 VDD - 0.6 550 10
V V ns k
Pin Descriptions
RST
The RST output is an open drain output, which is asserted low whenever the following occurs: 1. The device is initially powered up to 1V or 2. VDD, V2MON, V3MON or V4MON fall below their minimum voltage sense level.
RST VDD
V2MON MR
ISL88042
V3MON PB
RESET SIGNAL
MR
The MR input is an active low debounced input to which a user can connect a push-button to add manual reset capability or use a signal to pull low. MR has an internal pull-up resistor.
V4MON GND
FIGURE 1. TYPICAL APPLICATION DIAGRAM
VDD
The VDD pin is the IC power supply terminal. The voltage at this pin is compared against an internal factory-programmed voltage trip point, VTH1. RST is first asserted low when the device is initially powered and VDD < 1V and then at any time thereafter when VDD falls below VTH1. The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief power-supply transients.
Principles of Operation
The ISL88042 device provides those functions needed for monitoring critical voltages, such as power-supply and battery functions in microprocessor systems. It provides such features as Power-On Reset control, supply voltage supervision, and Manual Reset Assertion. The integration of all these features along with competitive reset threshold accuracy and low power consumption, makes the ISL88042 device suitable for a wide variety of applications needing multi-voltage monitoring. See Figure 1 for the "Typical Application Diagram".
V2MON
The V2MON input is the second preset monitored voltage that causes the RST output to go low when the voltage on V2MON falls below VTH2.
Low Voltage Monitoring
During normal operation, the ISL88042 monitors the voltage levels of VDD, V2MON, V3MON and V4MON. If the voltage on any of these four inputs falls below their respective voltage trip points, a reset is asserted (RST = low) to prevent the microprocessor from operating during a power failure or brownout condition. This reset signal remains low until the voltages exceeds the voltage threshold settings for the reset time delay period tPOR. The ISL88042 allows users to customize the minimum voltage sense level for two of the four monitored voltages. For example, the user can adjust the voltage input trip point (VTRIP) for the V3MON and V4MON inputs. To do this, connect an external resistor divider network to the VxMON pin in order to set the trip
V3MON, and V4MON
The VxMON inputs provide monitoring and UV compliance of three additional voltages through resistor dividers. A reset is issued on the ISL88042 if the voltage on any VxMON falls below the internal VREF of 0.6V.
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FN6655.1 June 8, 2009
ISL88042
point to some other voltage above 600mV according to Equation 1:
V TRIP = 0.6V x R 1 + R 2 / R 2 (EQ. 1)
The reset signal remains active until VDD rises above the minimum voltage sense level for time period tPOR. This ensures that the supply voltage has stabilized to sufficient operating levels.
Power-On Reset (POR)
Applying power to the ISL88042 activates a POR circuit, which makes the reset pin(s) active (i.e. RST goes high while RST goes low). These signals provide several benefits: * They prevent the system microprocessor from starting to operate with insufficient voltage. * They prevent the processor from operating prior to stabilization of the oscillator. * They ensure that the monitored device is held out of operation until internal registers are properly loaded. * They allow time for an FPGA to download its configuration prior to initialization of the circuit.
VTH1/VTH2 VDD / V2MON
Manual Reset
The manual-reset input (MR) allows the user to trigger a reset by using a push-button switch or by signaling the input low. The MR input is an active low debounced input. Reset is asserted if the MR pin is pulled low to less than 100mV for the minimum MR pulse width or longer while the push-button is closed. After MR is released, the reset output remains asserted low for tPOR (200ms) and then is released. Figures 2 and 3 illustrate the ISL88042's operation.
1V
>tMR
MR tPOR tRPD tPOR tPOR
RST
>tMD
FIGURE 2. POWER SUPPLY MONITORING DIAGRAM
VXMON VTH tRPD tPOR
RST
FIGURE 3. VOLTAGE MONITORING DIAGRAM
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ISL88042 The ISL88042EVAL1Z and Applications
The ISL88042EVAL1Z supports all variants of the ISL88042 devices, enabling evaluation of basic functional operation and common application implementations. Figure 10 illustrates the ISL88042EVAL1Z in schematic and photographic forms. The ISL88042EVAL1Z is populated with the ISL88042IRTEEZ (VDD VTH1 and V2MON VTH2 = 2.90V). With adequate bias on the two preset and the two adjustable monitor inputs the RST output will release to pull high indicating that all supplies are compliant for a minimum of tPOR. For the ISL88042EVAL1Z as shipped, the VDD and V2MON nominal thresholds are as previously noted with the voltage thresholds being monitored by V3MON and V4MON being left open for programming via the non populated resistor dividers.
Special Application Considerations
Using good decoupling practices on bias and other monitoring inputs will prevent transients (i.e. due to switching noises and short duration droops in the supply voltage) from causing unwanted resets. In unusually noisy environments or situations where unwanted signals may be injected into the adjustable VMON inputs, lowering the node impedance and/or positioning a small valued filter capacitor as close to the pin as possible can increase noise immunity. Although the internal ISL88042 threshold references are guaranteed over the full temp range, accuracy errors due to external component tolerances and distribution losses will occur. High tolerance resistors and layout for extreme accuracy and critical performance must be considered.
Typical Performance Curves
3.20 AVG. VDD AND V2MON Vth (V) 3.15 3.10 3.05 ISL88042IRTHF V2MON 3.00 2.95 2.90 2.85 2.80 -40 -20 0 25 50 85 TEMPERATURE (C) 100 125 ISL88042IRTEE VDD ISL88042IRTEE V2MON ISL88042IRTHF VDD 4.60 AVG. VXMON Vth (mV) 4.59 4.58 4.57 4.56 4.55 4.54 4.53 602 601 600 599 598 597 596 595 594 593 592 -40 -20 0 25 50 85 TEMPERATURE (C) 100 125 V3MON V4MON
FIGURE 4. VDD and V2MON Vth vs TEMPERATURE
FIGURE 5. V3MON and V4MON Vth vs TEMPERATURE
120 115 110 tPOR (ms) 105 100 95 90 85 80 -40 -20 0 25 50 85 TEMPERATURE (C) 100 125 BIAS CURRENT (A)
16 14 12 10 8 6 4 2 0 -40 -20 0 25 50 85 TEMPERATURE (C) 100 125 V2MON = 3.3V VDD = 5V
FIGURE 6. tpor vs TEMPERATURE
FIGURE 7. BIAS CURRENT vs TEMPERATURE
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ISL88042 Typical Performance Curves
RST 1V/DIV
RST 1V/DIV
tRPD = 4.3s
tPOR = 94ms
VMON = 0.5V/DIV
VMON = 0.5V/DIV
1s/DI
20ms/DIV
FIGURE 8. ISL88042 tRPD
FIGURE 9. ISL88042 tPOR
VDD
10k
U1 MRST C1 VDD A OPEN V2MON AGND A V2MON GND VDD MR RST
R2 RST R5 V4MON V4 OPEN R3 V3 OPEN V3MON OPEN OPEN R6 R4
V4MON V3MON
ISL88042
A
FIGURE 10. ISL88042EVAL1Z SCHEMATIC AND PHOTOGRAPH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN6655.1 June 8, 2009
ISL88042
Package Outline Drawing
L8.2x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE WITH E-PAD Rev 1, 06/09
6 PIN #1 INDEX AREA B 0.50 0.25
2.00
A
1.80 +0.1/ -0.15 1.65 +0.1/ -0.15
6 PIN 1 INDEX AREA
(4X)
0.15 (8x0.40)
TOP VIEW
3.00
BOTTOM VIEW
(8x0.25) PACKAGE OUTLINE (6x0.50)
2.20 SEE DETAIL "X" C BASE PLANE SEATING PLANE 0.08 C
0.75 0.05 3.00 1.80
SIDE VIEW
(8x0.40) 1.65 2.00 (8x0.20)
C
0.20 REF
5
0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension b applies to the metallized terminal and is measured between 0.20mm and 0.32mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
2. 3. 4.
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